Reg (EU) 2024/2847Generate dossier — €149
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Annex III of Regulation (EU) 2024/2847 classifies application-specific integrated circuits and field-programmable gate arrays with security-related functionalities as Important Class I products. Item 15 targets your product category directly. Your conformity assessment path is not Module A by default — it depends on whether harmonised standards cover your essential requirements. CRACheck documents the classification and generates the dossier.

If your ASIC implements a hardware root of trust, a crypto accelerator, a secure key storage vault, or a tamper-detection mesh, it has security-related functionalities under Annex III item 15. That classification as Important Class I means Module A self-assessment is available only if you apply harmonised standards covering all essential cybersecurity requirements of Annex I, or hold an EU cybersecurity certification at assurance level "substantial." Without either, Article 32(2) directs you to third-party assessment under Module B+C or Module H. CRACheck classifies your ASIC or FPGA, maps its security architecture to Annex I, and generates the 8-document dossier. €149. 15–25 minutes. Your design files stay on your machine.

Generate CRA dossier — €149Free: check your product classification

€149 one-time · 8-document ZIP · 15–25 minutes · Browser-side

Regulation (EU) 2024/2847 · Art. 31 + Annex VII · Annex III Class I item 15 · 8 documents · 100% browser-side

Key numbers

Item 15
Annex III Class I — ASICs and FPGAs with security functions
Art. 32(2)
Conformity assessment path for Important Class I
€149
Per ASIC/FPGA product family

How CRACheck works

You enter your product data. CRACheck structures the documentation per Article 31 + Annex VII.

1
Confirm your Annex III classification
CRACheck validates that your ASIC or FPGA's security functions place it under item 15 and determines whether Class I or Class II (tamper-resistant) applies
2
Define your hardware security architecture
Crypto engines, key management, secure boot chain, debug port protection, side-channel countermeasures
3
Document your design and verification process
RTL review, formal verification of security properties, production testing, supply chain integrity
4
Map Annex I essential requirements
How your ASIC/FPGA meets each cybersecurity requirement at the hardware implementation level
5
Complete vulnerability handling
Hardware errata process, security advisory issuance, coordination with integrators, ENISA notification readiness
6
Generate the 8-document dossier
Structured for your Annex III Class I position with references to the applicable conformity assessment path
7
Prepare for conformity assessment
The dossier is the documentation input for Module A (if standards apply) or Module B+C/H (if not)

Common mistakes

DEFAULT ASSUMPTION

"Our ASIC is custom silicon — it does not appear on any CRA list"

Annex III Class I item 15 explicitly lists "application specific integrated circuits (ASIC) and field-programmable gate arrays (FPGA) with security-related functionalities." The item targets the function, not the brand or specific product name. If your ASIC implements any security function — cryptographic processing, authentication, tamper detection, secure key storage — it matches this category.

FPGA RECONFIGURABILITY

"FPGAs are blank slates — the CRA applies to the bitstream, not the chip"

If the FPGA is manufactured and marketed with security-related functionalities (e.g., embedded crypto blocks, secure boot support, anti-tamper features), the FPGA itself is the product with digital elements. The manufacturer who designs and markets the FPGA with these features carries obligations under Article 13. A downstream user who loads a custom bitstream may become a manufacturer of a modified product under Article 22 if the modification is substantial.

COMMON CRITERIA SUBSTITUTION

"Our ASIC has a Common Criteria EAL4+ certificate — CRA conformity is covered"

A Common Criteria evaluation is not the same as CRA conformity assessment. Article 32(2) allows Module A for Important Class I products only with harmonised standards or an EU cybersecurity certification at assurance level "substantial" under the Cybersecurity Act (Regulation (EU) 2019/881). A CC certificate under a national scheme may support your case but does not automatically satisfy CRA requirements. A separate Annex VII dossier is still required.

What the ZIP contains

8 PDF documents generated from your data. Each cites the specific article of Regulation (EU) 2024/2847 it complies with.

1

Product Classifier

Determines whether your ASIC/FPGA is Important Class I (item 15, security functions), Class II (items 3–4, tamper-resistant), or another category. Documents the rationale and conformity assessment path.

2

Technical Documentation

Art. 31 + Annex VII dossier covering hardware architecture, security function specifications, design verification, production integrity controls.

3

Risk Assessment

Annex I Part I analysis at the hardware level: physical attacks, side-channel analysis, fault injection, reverse engineering, supply chain tampering.

4

User Information

Annex II information for integrators: secure integration guidelines, debug interface controls, key provisioning procedures, configuration requirements.

5

Declaration of Conformity

Art. 28 + Annex V with Annex III Class I classification and applicable conformity module.

6

CVD Policy

Hardware vulnerability disclosure: errata notification process, security advisory format, coordination with integrator ecosystem.

7

Notification Template

Art. 14 ENISA notification for hardware-level vulnerabilities. Art. 14(2): early warning within 24h, notification within 72h, final report within 14 days.

8

Obligations Calendar

Enforcement milestones, silicon revision schedule, support period.

Mira antes de comprar — Descargar dossier de muestra (PDF, empresa ficticia) — Estructura real, artículos reales, formato real. Datos ficticios.

Generated from your data, in your browser. No data leaves your device.

What you pay

🧾 SEMICONDUCTOR SECURITY COMPLIANCE SPECIALIST
€20,000–€40,000
10–20 weeks. Requires NDA + RTL-level design disclosure. Hardware-specific CRA expertise is rare — most consultants generalise. Output: consultant opinion, not structured regulatory dossier.
✓ CRACHECK
€149
8 documents. 15–25 min. 100% browser-side — your RTL and security architecture stay internal. 10 regenerations for silicon revisions. Pack 10: €99/product. Pack 30: €79/product.

Two layers

● LAYER 1

Classification and documentation

CRACheck confirms your Annex III position, structures your security architecture against Annex I essential requirements, and generates the 8-document dossier per Art. 31 + Annex VII. This documentation is the prerequisite for any conformity assessment path — Module A, B+C, or H.

∅ LAYER 2

Conformity assessment and certification

If harmonised standards do not cover your ASIC's essential requirements, Article 32(2) requires third-party assessment. CRACheck produces the documentation that feeds into that process. It does not submit applications to notified bodies, conduct side-channel evaluations, or manage your CC certification. Those are separate activities that require your documentation as input.

No conformity assessment begins without documentation. CRACheck produces that documentation. Start here.

Enforcement regime

Article 64 of Regulation (EU) 2024/2847.

🔴
Essential requirements + manufacturer obligations (Art. 64(2))
€15,000,000 / 2.5%

Annex I + Art. 13/14.

🟠
Documentation and conformity obligations (Art. 64(3))
€10,000,000 / 2%

Art. 28, 31, 32.

🟡
Misleading information (Art. 64(4))
€5,000,000 / 1%

Misleading information.

Alternatives

CriterionSemiconductor Security ConsultantCC Evaluation LabIn-House from StandardsCRACheck
Time per product10–20 weeks12–24 months (CC)8–16 weeks15–25 minutes
Cost€20,000–€40,000€100,000+ (CC eval)Staff + training€149
CRA-specific outputConsultant reportCC certificate (not CRA)Variable quality8 PDFs per Annex VII
IP exposureNDA + design filesNDA + test accessInternal100% browser-side

Multiple ASIC/FPGA families with security functions?

Each product family with distinct security architecture requires its own classification and dossier. Volume pricing: €99/product (pack 10), €79/product (pack 30).

Request Volume Pricing
Silicon revisions with unchanged security architecture can use regeneration within the same dossier.

What CRACheck guarantees and what it does not

CRACheck generates a structured document aligned with Article 31 and Annex VII of Regulation (EU) 2024/2847 based on your ASIC or FPGA product data. The accuracy of that data — including your product's security functionalities and design characteristics — is your responsibility as manufacturer.

We guarantee the document structure follows Art. 31 + Annex VII and that the Annex III classification logic is current. We do not guarantee acceptance by a notified body or market surveillance authority in a specific case.

CRACheck is not legal advice. For Annex III item 15 classification disputes, conformity assessment strategy, or interaction with CC evaluation schemes, consult a specialised regulatory attorney.

Frequently asked questions

What counts as "security-related functionality" for ASICs and FPGAs?
Annex III item 15 targets ASICs and FPGAs that implement functions directly related to cybersecurity: cryptographic processing, secure key storage, hardware root of trust, secure boot enforcement, tamper detection, anti-cloning measures. If your product datasheet lists any of these capabilities, it falls under this category.
Is a general-purpose FPGA without embedded security blocks covered?
If the FPGA does not have security-related functionalities as manufactured and marketed, it may not fall under Annex III item 15. However, it is still a product with digital elements under Article 3(1) if it contains firmware or establishes data connections — classified as Default. CRACheck evaluates this.
We sell our ASIC to a single customer under their spec. Are we still the manufacturer?
Article 3(13) defines the manufacturer as whoever develops or manufactures the product and markets it under their name or trademark. If you design and produce the ASIC and market it (even to a single customer) under your company name, you are the manufacturer. If the customer owns the design and you only fabricate, the analysis may differ — CRACheck's classifier helps determine this.
How does Annex III item 15 relate to tamper-resistant items in Class II?
Annex III Class I item 15 covers ASICs/FPGAs with security-related functionalities in general. Class II items 3 (tamper-resistant microprocessors) and 4 (tamper-resistant microcontrollers) are separate categories with stricter assessment requirements. If your ASIC is specifically designed for tamper resistance and functions as a microprocessor, it may fall under Class II instead. CRACheck distinguishes between these.
Is this a subscription?
No. One-time payment. 30 days editing, 10 regenerations. PDF yours permanently.
Can I request a refund?
Under Article 16(m) of Directive (EU) 2011/83, licence activation constitutes express consent. Refunds only for reproducible technical failures.
What if the regulation is amended?
Regenerate at no additional cost during licence validity.
⚠️ Important notice: CRACheck is a self-assessment documentation tool, not legal advice and not a third-party audit. The document under Article 31 and Annex VII of Regulation (EU) 2024/2847 is generated from your input data. You are responsible for the accuracy of the data you provide. CRACheck does not replace a qualified professional assessment.

Your ASIC is on the Annex III list. The documentation must exist before any assessment begins.

Eight documents. Article 31 + Annex VII fully structured. Regulation (EU) 2024/2847. Your data stays on your device. The ZIP you download is yours forever.

€149 one-time
8-document professional dossier · 15–25 minutes · No subscription · Browser-side
Generate CRA dossier — €149
✓ Last regulatory check: 1 May 2026 · No substantive changes detected · View history